S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 370

• Manufacturer Part Number: S9S12P64J0MFT
• Description: MCU 64K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12P64J0MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Communication Interface (S12SCIV5)
11.3.2.3
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
11.3.2.4
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
370
Module Base + 0x0000
Module Base + 0x0001
RXEDGIF
BERRIF
BERRV
Reset
Reset
BKDIF
Field
7
2
1
0
W
W
R
R
RXEDGIE
RXEDGIF
Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,
rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.
0 No active receive on the receive input has occurred
1 An active edge on the receive input has occurred
Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and
a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.
0 A low input was sampled, when a high was expected
1 A high input reassembled, when a low was expected
Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value
sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an
interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.
0 No mismatch detected
1 A mismatch has occurred
Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is
received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing
a “1” to it.
0 No break signal was received
1 A break signal was received
SCI Alternative Status Register 1 (SCIASR1)
SCI Alternative Control Register 1 (SCIACR1)
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 11-7. SCI Alternative Control Register 1 (SCIACR1)
Figure 11-6. SCI Alternative Status Register 1 (SCIASR1)
0
0
0
0
6
6
Table 11-6. SCIASR1 Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
0
0
0
0
5
5
0
0
0
0
4
4
Description
0
0
0
0
3
3
BERRV
0
0
0
2
2
BERRIE
BERRIF
Freescale Semiconductor
0
0
1
1
BKDIE
BKDIF
0
0
0
0