S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 162

• Manufacturer Part Number: S9S12P64J0MFT
• Description: MCU 64K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12P64J0MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12S Debug Module (S12SDBGV2)
6.3.2.4
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
162
Address: 0x0023
ABCM[1:0]
TRCMOD
TALIGN
Reset
Field
Field
3–2
1–0
0
W
R
ABCM
00
01
10
Trace Mode Bits — See
information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace
memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. In
Compressed Pure PC mode the program counter value for each instruction executed is stored. See
Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session.
0 Trigger at end of stored data
1 Trigger before storing data
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in
Debug Control Register2 (DBGC2)
0
0
7
TRCMOD
= Unimplemented or Reserved
00
01
10
11
Table
Match0 mapped to comparator A match: Match1 mapped to comparator B match.
0
0
6
Table 6-7. DBGTCR Field Descriptions (continued)
6-10.
Match 0 mapped to comparator A/B outside range: Match1 disabled.
Figure 6-6. Debug Control Register2 (DBGC2)
Table 6-8. TRCMOD Trace Mode Bit Encoding
Match 0 mapped to comparator A/B inside range: Match1 disabled.
6.4.5.2
S12P-Family Reference Manual, Rev. 1.13
Table 6-9. DBGC2 Field Descriptions
0
0
5
Table 6-10. ABCM Encoding
for detailed Trace Mode descriptions. In Normal Mode, change of flow
0
0
4
Compressed Pure PC
Description
Description
Description
Description
Normal
Loop1
Detail
0
0
3
0
0
2
Freescale Semiconductor
0
1
ABCM
Table
0
0
6-8.