MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 138

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Resets and Interrupts
13.2.3.1 Power-On Reset (POR)
A power-on reset (POR) is an internal reset caused by a positive transition on the V
POR must go completely to 0 V to reset the MCU. This distinguishes between a reset and a POR. The
POR is not a brown-out detector, low-voltage detector, or glitch detector.
A power-on reset:
13.2.3.2 Computer Operating Properly (COP) Reset
A COP reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP
bit in the system integration module (SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to the COP control register at location
$FFFF.
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Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles
Drives the RST pin low during the oscillator stabilization delay
Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
Sets the POR bit in the SIM reset status register and clears all other bits in the register
PORRST
CGMXCLK
INTERNAL
CGMOUT
1. PORRST is an internally generated power-on reset pulse.
CGMXCLK
INTERNAL
RST PIN
RESET
RST PIN
OSC1
RESET
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
(1)
Figure 13-2. Power-On Reset Recovery
Figure 13-1. Internal Reset Timing
CYCLES
PULLED LOW BY MCU
4096
32 CYCLES
CYCLES
32
CYCLES
32
32 CYCLES
Freescale Semiconductor
DD
pin. V
DD
at the