MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 87

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.3.5 Clock Selection Circuit
The clock selection circuit, shown in
output clock (CGMXCLK) and the timebase clock (TBMCLK) from either the internal clock (ICLK) or the
external clock (ECLK). The COP clock (COPCLK) is identical to TBMCLK. The clock selection circuit also
contains a divide-by-two circuit which creates the clock generator output clock (CGMOUT), which
generates the bus clocks.
Freescale Semiconductor
ESTBCLK
ECGEN
CMON
ECLK
IREF
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
RESET
NAME
NAME
ECGON
EOFF
ECLK
ICLK
IOFF
V
CS
NAME
NAME
SS
Figure 7-8. Clock Selection Circuit Block Diagram
Figure 7-7. External Clock Activity Detector
D
CK
DFFRS
CONFIG2 REGISTER BIT
TOP LEVEL SIGNAL
R
S
CONFIG2 REGISTER BIT
TOP LEVEL SIGNAL
Q
Figure
CK
7-8, contains two clock switches which generate the oscillator
SELECT
ICLK
ECLK
IOFF
EOFF
FORCE_I
FORCE_E
SELECT
ICLK
ECLK
IOFF
EOFF
FORCE_I
FORCE_E
1/4
R
Q
SYNCHRONIZING
SYNCHRONIZING
SWITCHER
SWITCHER
D
CK
CLOCK
CLOCK
DFFRR
R
R
Q
OUTPUT
OUTPUT
NAME
NAME
NAME
NAME
DIV2
REGISTER BIT
MODULE SIGNAL
MODULE SIGNAL
REGISTER BIT
CGMXCLK
CGMOUT
TBMCLK
COPCLK
EGGS
EOFF
Functional Description
87