MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 210

IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP

MCHC908GR8CFAE

Manufacturer Part Number
MCHC908GR8CFAE
Description
IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheets

Specifications of MCHC908GR8CFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
7.5KB (7.5K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
384Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08G
Core
HC08
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8.2 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Serial Peripheral Interface (SPI) Module
16.8 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is 0.
Whenever SPE is 0, the following occurs:
These items are reset only by a system reset:
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without
having to set all control bits again when SPE is set back high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the
SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be
disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
16.9 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
16.9.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt
requests by setting the error interrupt enable bit (ERRIE). See
16.9.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by
reset, any transfer in progress is aborted, and the SPI is reset.
16.10 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. BCFE in the SIM break flag control register (SBFCR) enables software to clear status bits
during the break state. See
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
210
The SPTE flag is set.
Any transmission currently in progress is aborted.
The shift register is cleared.
The SPI state counter is cleared, making it ready for a new complete transmission.
All the SPI port logic is defaulted back to being general-purpose I/O.
All control bits in the SPCR register
All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)
The status flags SPRF, OVRF, and MODF
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Chapter 15 System Integration Module (SIM).
16.7
Interrupts.
Freescale Semiconductor

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