MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 85

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

To conserve size, the long divider (divide by 4096) is also used as an external crystal stabilization divider.
The divider is reset when the external clock generator is turned off or in stop mode (ECGEN is clear).
When the external clock generator is first turned on, the external clock generator stable bit (ECGS) will
be clear. This condition automatically selects ECLK as the input to the long divider. The external
stabilization clock (ESTBCLK) will be ECLK divided by 16 when EXTXTALEN is low or 4096 when
EXTXTALEN is high. This timeout allows the crystal to stabilize. The falling edge of ESTBCLK is used to
set ECGS, which will set after a full 16 or 4096 cycles. When ECGS is set, the divider returns to its normal
function. ESTBCLK may be generated by either IBASE or ECLK, but any clocking will only reinforce the
set condition. If ECGS is cleared because the clock monitor determined that ECLK was inactive, the
divider will revert to a stabilization divider. Since this will change the EREF and IREF divide ratios, it is
important to turn the clock monitor off (CMON = 0) after inactivity is detected to ensure valid recovery.
Freescale Semiconductor
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
EXTSLOW
EXTXTALEN
NAME
ECGEN
NAME
ICGEN
CMON
FICGS
IBASE
ECLK
Figure 7-5. Clock Monitor Block Diagram
CONFIG2 REGISTER BIT
TOP LEVEL SIGNAL
FICGS
IBASE
ICGEN
EREF
IBASE
ICGON
EXTXTALEN
EXTSLOW
ECGS
ECLK
ECGEN
IREF
ECGEN
ECLK
CMON
CMON
ESTBCLK
DETECTOR
DETECTOR
ACTIVITY
ACTIVITY
ICLK
ECLK
GENERATOR
REFERENCE
ESTBCLK
EREF
ECGS
EOFF
IREF
IOFF
ICGS
NAME
NAME
MODULE SIGNAL
REGISTER BIT
ECGS
ICGS
EOFF
IOFF
Functional Description
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