MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 241
MCHC908GR8CFAE
Manufacturer Part Number
MCHC908GR8CFAE
Description
IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Specifications of MCHC908GR8CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
7.5KB (7.5K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
384Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08G
Core
HC08
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8.2 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCHC908GR8CFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MCHC908GR8CFAER
Manufacturer:
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Quantity:
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19.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
BRKE — Break Enable Bit
BRKA — Break Active Bit
19.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
Freescale Semiconductor
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to
bit 7. Reset clears the BRKE bit.
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
1 = (When read) Break address match
0 = (When read) No break address match
Address:
Address:
Address:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Figure 19-4. Break Status and Control Register (BRKSCR)
$FE0B
$FE0A
$FE09
BRKE
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
Figure 19-5. Break Address Register High (BRKH)
Figure 19-6. Break Address Register Low (BRKL)
= Unimplemented
BRKA
14
6
0
6
0
6
6
0
13
5
0
0
5
0
5
5
0
12
4
0
0
4
0
4
4
0
11
3
0
0
3
0
3
3
0
10
2
0
0
2
0
2
2
0
1
0
0
1
9
0
1
1
0
Break Module (BRK)
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
0
0
0
0
241
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