R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 325
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 288 of 802
19.5.4
Notes:
1. Enabled when in PWM mode.
2. Enabled when in output compare function, PWM mode, or PWM2 mode. For notes on PWM2 mode, refer to
3. Enabled when in PWM2 mode.
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0130h
19.9.5 TRCMR Register in PWM2 Mode .
Symbol TCEG1
Symbol
TCEG0 TRCTRG input edge select bit
TCEG1
Bit
POLB
POLC
POLD
CSEL
Timer RC Control Register 2 (TRCCR2) in Timer Mode (Output Compare
Function)
—
—
b7
0
PWM mode output level
control bit B
PWM mode output level
control bit C
PWM mode output level
control bit D
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
TRC count operation select bit
TCEG0
b6
0
Oct 30, 2009
(1)
(1)
(1)
Bit Name
CSEL
b5
0
b4
—
(3)
(2)
1
0: TRCIOB output level selected as low active
1: TRCIOB output level selected as high active
0: TRCIOC output level selected as low active
1: TRCIOC output level selected as high active
0: TRCIOD output level selected as low active
1: TRCIOD output level selected as high active
0: Count continues at compare match with
1: Count stops at compare match with
b7 b6
0 0: Trigger input from the TRCTRG pin disabled
0 1: Rising edge selected
1 0: Falling edge selected
1 1: Both edges selected
b3
—
1
the TRCGRA register
the TRCGRA register
POLD
b2
0
Function
POLC
b1
0
POLB
b0
0
19. Timer RC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
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