R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 813
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 776 of 802
35.20 Notes on Flash Memory
35.20.1 CPU Rewrite Mode
Table 35.2
FMR21, FMR22: Bits in FMR2 register
EW0
EW1
Mode
35.20.1.1 Prohibited Instructions
35.20.1.2 Interrupts
The following instructions cannot be used while the program ROM area is being rewritten in EW0 mode
because they reference data in the flash memory: UND, INTO, and BRK.
Tables 35.2 to 35.4 list CPU Rewrite Mode Interrupts (1), (2), and (3), respectively.
Data
flash
Program
ROM
Data
flash
Program
ROM
Erase/
Target
Write
CPU Rewrite Mode Interrupts (1)
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
During
auto-programming
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled)
During
auto-programming
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
During
auto-programming
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
During
auto-programming
or FMR22 = 0)
or FMR22 = 0)
or FMR22 = 0)
Status
Oct 30, 2009
When an interrupt request is acknowledged, interrupt handling is executed.
If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request),
the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory
suspends auto-erasure after td(SR-SUS).
If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request
disabled by interrupt request), set the FMR21 bit to 1 during interrupt handling. The flash
memory suspends auto-erasure after td(SR-SUS).
While auto-erasure is being suspended, any block other than the block during auto-
erasure execution can be read . Auto-erasure can be restarted by setting the FMR21 bit
to 0 (erase restart).
Interrupt handling is executed while auto-erasure or auto-programming is being
performed.
Usable by allocating a vector in RAM.
When an interrupt request is acknowledged, interrupt handling is executed.
If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory
suspends auto-erasure after td(SR-SUS).
If erase-suspend is required while the FMR22 bit is set to 0, set the FMR21 bit to 1 during
interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS).
While auto-erasure is being suspended, any block other than the block during auto-
erasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit
to 0.
Interrupt handling is executed while auto-erasure or auto-programming is being
performed.
Auto-erasure suspends after td(SR-SUS) and interrupt handling is executed. Auto-
erasure can be restarted by setting the FMR21 bit to 0 after interrupt handling completes.
While auto-erasure is being suspended, any block other than the block during auto-
erasure execution can be read.
Auto-erasure and auto-programming have priority and interrupt requests are put on
standby. Interrupt handling is executed after auto-erase and auto-program complete.
Maskable Interrupt
35. Usage Notes
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