R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 605
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 568 of 802
26.4.3.1
Data transmission/reception is an operation combining data transmission and reception which were described
earlier. Transmission/reception is started by writing data to the SSTDR register.
When the last transfer clock (the data transfer length can be set from 8 to 16 bits using the SSBR register) rises
or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data transferred from registers SSTDR
to SSTRSR), the transmit/receive operation is stopped.
Before switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (TE = RE =
1), set the TE bit to 0 and RE bit to 0 once. After confirming that the TEND bit is set to 0 (TDRE bit is set to 0
when the last bit of the transmit data is transmitted), the RDRF bit is set to 0 (no data in the SSRDR register),
and the ORER bit is set to 0 (no overrun error), set bits TE and RE to 1.
Figure 26.9 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication
Mode).
When exiting transmit/receive mode after this mode is used (TE = RE = 1), a clock may be output if
transmit/receive mode is exited after reading the SSRDR register. To avoid any clock outputs, perform either of
the following:
- First set the RE bit to 0, and then set the TE bit to 0.
- Set bits TE and RE at the same time.
When subsequently switching to receive mode (TE = 0 and RE = 1), first set the SRES bit to 1, and set this bit
to 0 to reset the SSU control unit and the SSTRSR register. Then, set the RE bit to 1.
Data Transmission/Reception
Oct 30, 2009
26. Synchronous Serial Communication Unit (SSU)
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