R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 664
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 627 of 802
28.5
Table 28.2
Synch Break detection
Completion of Synch
Break generation
Completion of Synch
Field measurement
Bus collision detection
There are four interrupt requests generated by the hardware LIN: Synch Break detection, completion of Synch
Break generation, completion of Synch Field measurement, and bus collision detection. These interrupts are shared
with timer RA.
Table 28.2 lists the Hardware LIN Interrupt Requests.
Interrupt Request
Interrupt Requests
Hardware LIN Interrupt Requests
Oct 30, 2009
Status Flag
BCDCT
SBDCT
SFDCT
Generated when timer RA underflows after the low-level
duration for the RXD0 input is measured. Or when a low-
level signal is input for a duration longer than the Synch
Break period during communication.
Generated when the low-level output to TXD0 for the
duration set by timer RA is completed.
Generated when measurement for 6 bits of the Lynch Field
by timer RA is completed.
Generated when the RXD0 input and TXD0 output values
are different at the data latch timing while UART0 is enabled
for transmission.
Interrupt Source
28. Hardware LIN
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