R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 204
![MCU FLASH 48K 2.5K CMOS 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21217JFP#U1
Manufacturer Part Number
R5F21217JFP#U1
Description
MCU FLASH 48K 2.5K CMOS 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/21r
Datasheet
1.R5F21216JFP.pdf
(503 pages)
Specifications of R5F21217JFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21217JFP#U1R5F21217JFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.48
Timer RD Start Register
Timer RD Mode Register
b7 b6 b5 b4 b3 b2
NOTES:
b7 b6 b5 b4 b3 b2
NOTE:
1.
2.
3.
4.
5.
1. When selecting 0 (change the TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi (i = 0 or 1)
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1
TRDSTR Register of Notes on Tim er RD .
When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
When the CSEL0 bit is set to 0 and generating the compare match signal (TRDIOA0), this bit is set to 0 (count stops).
When the CSEL1 bit is set to 0 and generating the compare match signal (TRDIOA1), this bit is set to 0 (count stops).
register, set the BFji bit in the TRDMR register to 0.
Registers TRDSTR and TRDMR in Output Compare Function
b1 b0
b1 b0
Bit Symbol
Bit Symbol
TSTART0
TSTART1
(b7 - b4)
(b3 - b1)
TRDSTR
Symbol
Symbol
TRDMR
CSEL0
CSEL1
SYNC
Page 186 of 458
BFC0
BFD0
BFC1
BFD1
(1)
—
—
TRD0 count start flag
TRD1 count start flag
TRD0 count operation select
bit
TRD1 count operation select
bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Timer RD synchronous bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRDGRC0 register function
selection bit
TRDGRD0 register function
selection bit
TRDGRC1 register function
selection bit
TRDGRD1 register function
selection bit
Address
Bit Name
0137h
(1)
(1)
(1)
(1)
Address
Bit Name
0138h
(4)
(5)
0 : Count stops
1 : Count starts
0 : Count stops
1 : Count starts
0 : Count stops at the compare match w ith
1 : Count continues at the compare match w ith
0 : Count stops at the compare match w ith
1 : Count continues at the compare match w ith
the TRDGRA0 register after the count clear
the TRDGRA0 register after the count clear
the TRDGRA1 register after the count clear
the TRDGRA1 register after the count clear
0 : TRD0 and TRD1 registers
1 : TRD0 and TRD1 registers
0 : General register
1 : Buffer register of TRDGRA0 register
0 : General register
1 : Buffer register of TRDGRB0 register
0 : General register
1 : Buffer register of TRDGRA1 register
0 : General register
1 : Buffer register of TRDGRB1 register
operate independently
operate synchronously
(2)
(3)
After Reset
11111100b
Function
After Reset
00001110b
Function
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
—
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