R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 365
![MCU FLASH 48K 2.5K CMOS 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21217JFP#U1
Manufacturer Part Number
R5F21217JFP#U1
Description
MCU FLASH 48K 2.5K CMOS 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/21r
Datasheet
1.R5F21216JFP.pdf
(503 pages)
Specifications of R5F21217JFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21217JFP#U1R5F21217JFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
17.3
Figure 17.2
LIN Control Register
The hardware LIN contains the following registers.
Figure 17.2 and Figure 17.3 show the LINCR and LINST Registers.
b7 b6 b5 b4
NOTES:
•
•
1.
2.
3. Input to timer RA and UART0 are prohibited immediately after the LINE bit is set to 1(Causes LIN to start operating).
LIN Control Register (LINCR)
LIN Status Register (LINST)
Register Configuration
After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0).
Refer to Figure 17.5 Exam ple of Header Field Transm ission Flow chart (1) and Figure 17.9 Exam ple of
Header Field Reception Flow chart (2).
b3 b2 b1 b0
LINCR Register
Bit Symbol
LSTART
Symbol
RXDSF
LINCR
SFIE
SBIE
BCIE
MST
Page 347 of 458
SBE
LINE
Synch Field measurement-
completed interrupt enable bit
Synch Break detection interrupt
enable bit
Bus collision detection interrupt
enable bit
RxD0 input status flag
Synch Break detection start bit
RxD0 input unmasking timing
select bit
(effective in only slave mode)
LIN operation mode setting bit
LIN operation start bit
Address
Bit Name
0106h
(2)
(1)
0 : Disables Synch Field measurement-
1 : Enables Synch Field measurement-
0 : Disables Synch Break detection interrupt
1 : Enables Synch Break detection interrupt
0 : Disables bus collision detection interrupt
1 : Enables bus collision detection interrupt
0 : RXD0 input enabled
1 : RXD0 input disabled
When this bit is set to 1, Timer RA input is
enabled and RXD0 input is disabled.
When read, its content is 0.
0 : Unmasked after Synch Break is detected
1 : Unmasked after Synch Field measurement
0 : Slave mode
1 : Master mode
0 : Causes LIN to stop
1 : Causes LIN to start operating
completed interrupt
completed interrupt
is completed
(Synch Break detection circuit actuated)
(timer RA output OR’ed w ith TxD0)
After Reset
Function
00h
(3)
17. Hardware LIN
WO
RW
RW
RW
RW
RW
RW
RW
RO
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