R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 354

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 16.42
16.3.4.2
In transmit mode, transmit data is output from the SDA pin synchronizing with the fall of the transfer clock.
The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is
set to 0.
Figure 16.42 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode).
The transmit procedure and operation in transmit mode are shown below.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set the CKS0 to CKS3 bits in the
(2) The TDRE bit in the ICSR register is set to 1 by selecting transmit mode after setting the TRS bit in the
(3) Data is transferred from the ICDRT to ICDRS registers and the TDRE bit is automatically set to 1 by
ICDRT register
ICDRS register
ICCR1 register
ICSR register
by program
TDRE bit in
TRS bit in
Process
(output)
ICCR1 register and set the MST bit (initial setting).
ICCR1 register to 1.
writing transmit data to the ICDRT register after confirming that the TDRE bit is set to 1. When writing
data to the ICDRT register every time the TDRE bit is set to 1, the continuous transmit is enabled. When
switching from transmit to receive modes, set the TRS bit to 0 while the TDRE bit is set to 1.
SDA
SCL
Transmit Operation
Operating Timing in Transmit Mode (Clock Synchronous Serial Mode)
(2) Set TRS bit to 1
1
0
1
0
(3) Data write to
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ICDRT register
Data 1
b0
Data 1
1
b1
(3) Data write to
2
ICDRT register
b6
Data 2
7
b7
8
b0
Data 2
1
16. Clock Synchronous Serial Interface
(3) Data write to
ICDRT register
b6
7
b7
8
(3) Data write to
Data 3
ICDRT register
Data 3
b0
1