R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 399

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 19.4
19.3.2
Option Function Select Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
1.
2.
3.
The ROM code protect function disables to read and change the internal flash memory by the OFS register in
parallel I/O mode.
Figure 19.4 shows the OFS Register.
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit and
disables to read and change the internal flash memory.
Once the ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel
I/O mode. When the ROM code protect is disabled, erase the block including the OFS register with CPU
rewrite mode or standard serial I/O mode.
1 1
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
To use the pow er-on reset, set the LVD1ON bit to 0 (voltage monitor 1 reset enabled after reset).
If the block including the OFS register is erased, FFh is set to the OFS register.
ROM Code Protect Function
OFS Register
1
Bit Symbol
CSPROINI
ROMCP1
LVD1ON
WDTON
ROMCR
(b5-b4)
Symbol
Page 381 of 458
OFS
(b1)
—
—
Watchdog timer start
select bit
Reserved bit
ROM code protect
disabled bit
ROM code protect bit
Reserved bits
Voltage detection circuit
start bit
Count source protect
mode after reset select
bit
(1)
(2)
Address
Bit Name
0FFFFh
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Set to 1
0 : ROM code protect disabled
1 : ROMCP1 enabled
0 : ROM code protect enabled
1 : ROM code protect disabled
Set to 1
0 : Voltage monitor 1 reset enabled after reset
1 : Voltage monitor 1 reset disabled after reset
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
Before Shipment
Function
FFh
(3)
19. Flash Memory
RW
RW
RW
RW
RW
RW
RW
RW