R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 499
![MCU FLASH 48K 2.5K CMOS 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21217JFP#U1
Manufacturer Part Number
R5F21217JFP#U1
Description
MCU FLASH 48K 2.5K CMOS 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/21r
Datasheet
1.R5F21216JFP.pdf
(503 pages)
Specifications of R5F21217JFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21217JFP#U1R5F21217JFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev.
1.10
REVISION HISTORY
Oct 31, 2007
Date
Page
316
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386
388
Figure 16.25; NOTE5 deleted.
Figure 16.26; NOTE3 revised and NOTE7 deleted.
Figure 16.27; NOTE3 deleted.
Figure 16.28; NOTE7 revised.
Figure 16.32 revised.
Figure 16.33 and Figure 16.34 revised.
Figure 16.35 revised.
Figure 16.36 revised.
16.3.8.1 replaced and 16.3.8.2 added.
Figure 17.5; Procedure of Hardware LIN Clear the status flags:
“LINST register ← 0” → “LINST register ← 1”
Figure 17.7 revised.
Figure 17.8; Bit name in the TRAMR register:
“MOD0 to 2 bits” → “Bits TMOD0 to TMOD2”
Figure 17.9; Procedure of Hardware LIN Clear the status flags:
“LINST register ← 0” → “LINST register ← 1”
Figure 17.11; Bit name in the LINST register:
“SCDCT flag” → “BCDCT flag”
Figure 17.12; Procedure of Hardware LIN Clear the status flags:
“LINST register ← 0” → “LINST register ← 1”
Figure 18.2; NOTE4 revised.
Table 18.2; Stop Condition revised.
Figure 18.4; NOTE4 revised.
Figure 18.6; NOTE4 revised.
Figure 18.10 revised. SW5 added.
18.6; the six line from the bottom:
“A/D conversion mode with” → “A/D conversion mode without”
18.7 revised.
Table 19.2; Function of CPU Rewrite Mode:
“any area other than the flash memory” → “the RAM”
Figure 19.4; NOTE1 revised.
Table 19.3; EW1 Mode:
“ROM area” → “ROM or RAM area”
19.4.1 and 19.4.2;
“td(SR-ES)” → “td(SR-SUS)”
19.4.2.4; the third line from the top:
“in other than the flash memory” → “transferred to the RAM”
19.4.2.15 revised.
Figure 19.5; NOTE3 and NOTE5 revised.
Figure 19.7; NOTE5 revised.
R8C/20 Group, R8C/21 Group Hardware Manual
C - 23
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