MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 1002
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
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Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale Semiconductor
Quantity:
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Port S pins 7–4 are associated with the SPI0. The SPI0 pin configuration is determined by several status
bits in the SPI0 module. Refer to SPI section for details. When not used with the SPI0, these pins can be
used as general purpose I/O.
Port S bits 3–0 are associated with the SCI1 and SCI0. The SCI ports associated with transmit pins 3 and
1 are configured as outputs if the transmitter is enabled. The SCI ports associated with receive pins 2 and
0 are configured as inputs if the receiver is enabled. Refer to SCI section for details. When not used with
the SCI, these pins can be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
24.0.5.20 Port S Input Register (PTIS)
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This also can be used to detect
overload or short circuit conditions on output pins.
24.0.5.21 Port S Data Direction Register (DDRS)
Read: Anytime.
Write: Anytime.
This register configures each port S pin as either input or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
1004
Reset
Reset
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
W
associated pin values.
W
R
R
1
DDRS7
PTIS7
—
0
7
7
= Unimplemented or Reserved
DDRS6
PTIS6
—
0
6
6
Figure 24-23. Port S Data Direction Register (DDRS)
Figure 24-22. Port S Input Register (PTIS)
DDRS5
MC9S12XDP512 Data Sheet, Rev. 2.21
PTIS5
—
0
5
5
DDRS4
PTIS4
—
0
4
4
DDRS3
PTIS3
—
0
3
3
DDRS2
PTIS2
—
0
2
2
DDRS1
Freescale Semiconductor
PTIS1
—
0
1
1
DDRS0
PTIS0
—
0
0
0
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