MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 919
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
490
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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PB[7:0]
PA[7:0]
Reset
Reset
Field
23.0.5.2
Read: Anytime.
Write: Anytime.
Field
23.0.5.3
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in
all other modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
7–0
7–0
W
W
R
R
DDRA7
Port A — Port A pins 7–0 are associated with address outputs ADDR15 through ADDR8 respectively inexpanded
modesWhen this port is not used for external addresses, these pins can be used as general purpose I/O. If the
data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register,
otherwise the buffered pin input state is read.
PB7
Port B — Port B pins 7–0 are associated with address outputs ADDR7 through ADDR1 respectively in expanded
modes. Pin 0 is associated with output ADDR0 in emulation modes and special test mode and with Upper Data
Select (UDS) in normal expanded mode. When this port is not used for external addresses, these pins can be
used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read
returns the value of the port register, otherwise the buffered pin input state is read.
7
0
7
0
Port B Data Register (PORTB)
Port A Data Direction Register (DDRA)
DDRA6
PB6
0
0
6
6
Figure 23-5. Port A Data Direction Register (DDRA)
Figure 23-4. Port B Data Register (PORTB)
Table 23-5. PORTB Field Descriptions
Table 23-4. PORTA Field Descriptions
DDRA5
PB5
5
0
5
0
DDRA4
PB4
0
0
4
4
Description
Description
DDRA3
PB3
3
0
3
0
DDRA2
PB2
0
0
2
2
DDRA1
PB1
1
0
1
0
DDRA0
PB0
0
0
0
0
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