MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 473
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10.4.7.2
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXEx flag of the empty message buffer is set.
10.4.7.3
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO.
This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are
multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the
foreground buffer.
10.4.7.4
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCAN internal sleep mode.
WUPE (see
10.4.7.5
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition
occurrs.
conditions:
10.4.7.6
Interrupts are directly associated with one or more status flags in either the
Receiver Flag Register
Freescale Semiconductor
•
•
Overrun — An overrun condition of the receiver FIFO as described in
Structures,” occurred.
CAN Status Change — The actual value of the transmit and receive error counters control the
CAN bus state of the MSCAN. As soon as the error counters skip into a critical range
(Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change,
which caused the error condition, is indicated by the TSTAT and RSTAT flags (see
Section 10.3.2.5, “MSCAN Receiver Flag Register
Receiver Interrupt Enable Register
Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)
Section 10.3.2.1, “MSCAN Control Register 0
Wake-Up Interrupt (WUPIF)
Error Interrupts Interrupt (CSCIF, OVRIF)
Receive Interrupt (RXF)
Transmit Interrupts (TXE[2:0])
Transmit Interrupt
Receive Interrupt
Wake-Up Interrupt
Error Interrupt
Interrupt Acknowledge
The dedicated interrupt vector addresses are defined in the
Interrupts
(CANRFLG)” or the
Interrupt Source
chapter.
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 10-37. Interrupt Vectors
(CANRIER)”).
Section 10.3.2.7, “MSCAN Transmitter Flag Register
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
NOTE
CCR Mask
I bit
I bit
I bit
I bit
(CANRFLG)” and
(CANCTL0)”) must be enabled.
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CANTIER (TXEIE[2:0])
Local Enable
Resets and
indicates one of the following
Section 10.3.2.5, “MSCAN
Section 10.3.2.6, “MSCAN
Section 10.4.2.3, “Receive
473
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