MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 182
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MC9S12XA512CAG
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.4.2.2
The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are
multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external
input data that can be accessed through the digital port register PORTAD (input-only).
The analog/digital multiplex operation is performed in the input pads. The input pad is always connected
to the analog inputs of the ATD. The input pad signal is buffered to the digital port registers. This buffer
can be turned on or off with the ATDDIEN register. This is important so that the buffer does not draw
excess current when analog potentials are presented at its input.
5.4.2.3
The ATD can be configured for lower MCU power consumption in 3 different ways:
Note that the reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the
power down state.
5.5
At reset the ATD is in a power down state. The reset state of each individual bit is listed within the Register
Description section (see
and their bit-field.
5.6
The interrupt requested by the ATD is listed in
vector address and priority.
See register descriptions for further details.
182
1. Stop mode: This halts A/D conversion. Exit from stop mode will resume A/D conversion, but due
2. Wait mode with AWAI = 1: This halts A/D conversion. Exit from wait mode will resume A/D
3. Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D
to the recovery time the result of this conversion should be ignored.
conversion, but due to the recovery time the result of this conversion should be ignored.
conversion in progress.
Resets
Interrupts
General Purpose Digital Input Port Operation
Low Power Modes
Section 5.3, “Memory Map and Register
Sequence complete
Interrupt Source
interrupt
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 5-24. ATD Interrupt Vectors
Table
Mask
CCR
I bit
5-24. Refer to the device overview chapter for related
ASCIE in ATDCTL2
Local Enable
Definition”), which details the registers
Freescale Semiconductor
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