MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 107
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
490
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
CME
0
1
1
1
SCME
X
0
1
1
SCMIE
X
X
0
1
Clock failure -->
Clock failure -->
Clock failure -->
Clock failure -->
SCMIF generates self clock mode wakeup interrupt.
Table 2-12. Outcome of Clock Loss in Wait Mode
Scenario 1: OSCCLK recovers prior to exiting wait mode.
Scenario 2: OSCCLK does not recover prior to exiting wait mode.
No action, clock loss not detected.
CRG performs Clock Monitor Reset immediately
Some time later OSCCLK recovers.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
or an External Reset is applied.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
or an External RESET is applied.
– MCU remains in wait mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– Set SCMIF interrupt flag.
– CM no longer indicates a failure,
– 4096 OSCCLK cycles later clock quality check indicates clock o.k.,
– SCM deactivated,
– PLL disabled depending on PLLWAI,
– VREG remains enabled (never gets disabled in wait mode).
– MCU remains in wait mode.
– Exit wait mode using OSCCLK as system clock (SYSCLK),
– Continue normal operation.
– Exit wait mode using OSCCLK as system clock,
– Start reset sequence.
– MCU remains in wait mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– Set SCMIF interrupt flag,
– Keep performing clock quality checks (could continue infinitely) while in wait mode.
– Exit wait mode in SCM using PLL clock (f
– Continue to perform additional clock quality checks until OSCCLK is o.k. again.
– Exit wait mode in SCM using PLL clock (f
– Start reset sequence,
– Continue to perform additional clock quality checks until OSCCLKis o.k.again.
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– SCMIF set.
– Exit wait mode in SCM using PLL clock (f
– Continue to perform a additional clock quality checks until OSCCLK is o.k. again.
MC9S12XDP512 Data Sheet, Rev. 2.21
CRG Actions
Chapter 2 Clocks and Reset Generator (S12CRGV6)
SCM
SCM
SCM
) as system clock,
) as system clock,
) as system clock,
107
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