MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 138
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
490
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Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale Semiconductor
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.5
This register selects the conversion clock frequency, the length of the second phase of the sample time and
the resolution of the A/D conversion (i.e., 8-bits or 10-bits). Writes to this register will abort current
conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
138
SMP[1:0]
PRS[4:0]
Reset
SRES8
Field
6:5
4:0
W
7
R
SRES8
ATD Control Register 4 (ATDCTL4)
0
7
A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The
A/D converter has an accuracy of 10 bits. However, if low resolution is required, the conversion can be speeded
up by selecting 8-bit resolution.
0 10 bit resolution
1 8 bit resolution
Sample Time Select —These two bits select the length of the second phase of the sample time in units of ATD
conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value
(bits PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles
long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine’s storage node. The
second phase attaches the external analog signal directly to the storage node for final charging and high
accuracy.
ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock
Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler
frequency is calculated as follows:
value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12.
Table 4-13
SMP1
Table 4-12
0
0
1
1
SMP1
0
6
ATDclock
illustrates the divide-by operation and the appropriate range of the bus clock.
Figure 4-7. ATD Control Register 4 (ATDCTL4)
lists the lengths available for the second sample phase.
Table 4-11. ATDCTL4 Field Descriptions
SMP0
MC9S12XDP512 Data Sheet, Rev. 2.21
SMP0
=
Table 4-12. Sample Time Select
0
1
0
1
0
5
------------------------------- -
BusClock
PRS
+
1
PRS4
0
4
Length of 2nd Phase of Sample Time
0.5
16 A/D conversion clock periods
Description
2 A/D conversion clock periods
4 A/D conversion clock periods
8 A/D conversion clock periods
PRS3
0
3
PRS2
1
2
Freescale Semiconductor
PRS1
0
1
PRS0
1
0
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