MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 645

• Manufacturer Part Number: MC9S12XA512CAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any
PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in
emulation modes.
A summary of PRR accesses is the following:
Freescale Semiconductor
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•
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An aligned word access to a PRR will take 2 bus cycles.
A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the
misaligned word access is not a PRR, the access will take only 3 cycles.
A byte access to a PRR will take 2 cycles.
PRR Name
MMCCTL0
MMCCTL1
ECLKCTL
Reserved
Reserved
EBICTL0
EBICTL1
PORTC
PORTD
PORTB
PORTE
PORTK
PORTA
RDRIV
MODE
DDRA
DDRB
DDRC
DDRD
DDRE
PUCR
DDRK
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 17-22. PRR Listing
PRR Local Address
$000C
$000D
$001C
$001D
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000E
$000F
$0012
$0013
$0032
$0033
Chapter 17 Memory Mapping Control (S12XMMCV2)
PRR Location
MMC
MMC
MMC
MMC
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
EBI
EBI
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