MC9S12XDT256MAG Freescale Semiconductor, MC9S12XDT256MAG Datasheet - Page 343

• Manufacturer Part Number: MC9S12XDT256MAG
• Description: IC MCU 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (24-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.2.25
Read: Anytime
Write: Anytime
All bits reset to zero.
Freescale Semiconductor
PTPS[7:0]
PTPS7
Reset
LATQ
Field
Field
7:0
0
0
0
0
0
0
0
0
W
R
PTPS7
Input Control Latch or Queue Mode Enable — The BUFEN control bit should be set in order to enable the IC
and pulse accumulators holding registers. Otherwise LATQ latching modes are disabled.
Write one into ICLAT bit in MCCTL, when LATQ and BUFEN are set will produce latching of input capture and
pulse accumulators registers into their holding registers.
0 Queue mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input
1 Latch mode is enabled. Latching function occurs when modulus down-counter reaches zero or a zero is
Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.
These are effective only when the PRNT bit of TSCR1 is set to 1.
this case.
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter
stages equal zero.
Precision Timer Prescaler Select Register (PTPSR)
0
7
PTPS6
pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding
register and the IC register memorizes the new timer value.
written into the count register MCCNT (see
the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit pulse
accumulators are cleared.
Table 7-32. Precision Timer Prescaler Selection Examples when PRNT = 1
0
0
0
0
0
0
0
Figure 7-47. Precision Timer Prescaler Select Register (PTPSR)
PTPS6
PTPS5
0
6
0
0
0
0
0
0
0
Table 7-30. ICSYS Field Descriptions (continued)
Table 7-31. PTPSR Field Descriptions
PTPS5
MC9S12XDP512 Data Sheet, Rev. 2.21
PTPS4
0
5
0
0
0
0
0
0
0
PTPS4
PTPS3
0
4
0
0
0
0
0
0
0
Section 7.4.1.1.2, “Buffered IC
Description
Description
PTPS2
PTPS3
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
0
0
0
0
1
1
1
0
3
Table 7-32
PTPS1
PTPS2
0
0
1
1
0
0
1
0
2
shows some selection examples in
Channels”). With a latching event
PTPS0
PTPS1
0
1
0
1
0
1
0
0
1
Prescale
Factor
PTPS0
1
2
3
4
5
6
7
0
0
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