MC9S12XDT256MAG Freescale Semiconductor, MC9S12XDT256MAG Datasheet - Page 947

IC MCU 256K FLASH 144-LQFP

MC9S12XDT256MAG

Manufacturer Part Number
MC9S12XDT256MAG
Description
IC MCU 256K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256MAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Operating Supply Voltage
0 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (24-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XDT256MAG
Manufacturer:
FREESCALE
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1 800
Part Number:
MC9S12XDT256MAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDT256MAG
Manufacturer:
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Quantity:
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DDRH[7:0]
RDRH[7:0]
Reset
Reset
Field
23.0.5.49 Port H Reduced Drive Register (RDRH)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each Port H output pin as either full or reduced. If the
port is used as input this bit is ignored.
Field
23.0.5.50 Port H Pull Device Enable Register (PERH)
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as
input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled.
7–0
7–0
W
W
R
R
RDRH7
PERH7
Data Direction Port H
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Reduced Drive Port H
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
7
0
7
0
on PTH or PTIH registers, when changing the DDRH register.
RDRH6
PERH6
Figure 23-52. Port H Pull Device Enable Register (PERH)
0
0
6
6
Figure 23-51. Port H Reduced Drive Register (RDRH)
Table 23-45. DDRH Field Descriptions
Table 23-46. RDRH Field Descriptions
RDRH5
PERH5
5
0
5
0
RDRH4
PERH4
0
0
4
4
Description
Description
RDRH3
PERH3
3
0
3
0
RDRH2
PERH2
0
0
2
2
RDRH1
PERH1
1
0
1
0
RDRH0
PERH0
0
0
0
0

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