MC9S12XDT256MAG Freescale Semiconductor, MC9S12XDT256MAG Datasheet - Page 787

• Manufacturer Part Number: MC9S12XDT256MAG
• Description: IC MCU 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (24-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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2
3
Freescale Semiconductor
RE
ADDR[22:20]
ACC[2:0]
ADDR[19:16]
IQSTAT[3:0]
ADDR[15:1]
IVD[15:1]
ADDR0
IVD0
UDS
LSTRB
LDS
R/W
WE
DATA[15:8]
DATA[7:0]
EWAIT
All inputs are capable of reducing input threshold level
Time-multiplex means that the respective signals share the same pin on chip level and are active alternating in a dedicated
time slot (in modes where applicable).
Function-multiplex means that one of the respective signals sharing the same pin on chip level continuously uses the pin
depending on configuration and reset state.
Signal
I
1
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
/O
I
(F)unction
EBI Signal
—
—
—
—
—
—
—
—
—
Multiplex
T
T
T
T
(T)ime
Table 21-1. External System Signals Associated with XEBI
2
—
—
—
—
—
—
—
—
—
—
F
F
F
3
Read Enable, indicates external read access
External address
Access source
External address
Instruction Queue Status
External address
Internal visibility read data (IVIS = 1)
External address
Internal visibility read data (IVIS = 1)
Upper Data Select, indicates external access
to the high byte DATA[15:8]
Low Strobe, indicates valid data on DATA[7:0]
Lower Data Select, indicates external access
to the low byte DATA[7:0]
Read/Write, indicates the direction of internal
data transfers
Write Enable, indicates external write access
Bidirectional data (even address)
Bidirectional data (odd address)
External control for external bus access
stretches (adding wait states)
MC9S12XDP512 Data Sheet, Rev. 2.21
Description
Chapter 21 External Bus Interface (S12XEBIV2)
NS
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
SS
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Available in Modes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NX
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ES
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
EX
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ST
No
No
No
No
No
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