MC9S12XDT256MAG Freescale Semiconductor, MC9S12XDT256MAG Datasheet - Page 951

• Manufacturer Part Number: MC9S12XDT256MAG
• Description: IC MCU 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (24-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset
Reset
23.0.5.55 Port J Input Register (PTIJ)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can be used to detect
overload or short circuit conditions on output pins.
23.0.5.56 Port J Data Direction Register (DDRJ)
Read: Anytime.
Write: Anytime.
This register configures each port J pin as either input or output.
The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6
(RXCAN4). The IIC takes control of the I/O if enabled. In these cases the data direction bits will
not change.
The SCI2 forces the I/O state to be an output for each port line associated with an enabled output
(TXD2). It also forces the I/O state to be an input for each port line associated with an enabled input
(RXD2). In these cases the data direction bits will not change.
The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
W
associated pin values.
W
R
R
1
DDRJ7
PTIJ7
7
0
7
0
= Unimplemented or Reserved
= Unimplemented or Reserved
DDRJ6
PTIJ6
0
0
6
6
Figure 23-58. Port J Data Direction Register (DDRJ)
Figure 23-57. Port J Input Register (PTIJ)
DDRJ5
PTIJ5
5
0
5
0
DDRJ4
PTIJ4
0
0
4
4
3
0
0
3
0
0
DDRJ2
PTIJ2
0
0
2
2
DDRJ1
PTIJ1
1
0
1
0
DDRJ0
PTIJ0
0
0
0
0