M30280FAHP#D5 Renesas Electronics America, M30280FAHP#D5 Datasheet - Page 210
M30280FAHP#D5
Manufacturer Part Number
M30280FAHP#D5
Description
IC M16C MCU FLASH 96K 80-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30280FAHP#D5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
For Use With
M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
M30280FAHP#D5A
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1
Figure 14.18 Transfer Format
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J
6
0
C
2
9
2 /
0 .
B
14.1.2.2 Counter Measure for Communication Error
14.1.2.3 LSB First/MSB First Select Function
0
8
0
0
If a communication error occurs while transmitting or receiving in UART mode, follow the procedure
below.
• Resetting the UiRB register (i=0 to 2)
• Resetting the UiTB register (i=0 to 2)
As shown in Figure 14.18, use the UFORM bit in the UiC0 register to select the transfer format. This
function is valid when transfer data is 8 bits long.
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the RE bit in the UiC1 register to “1” (reception enabled)
(1) Set the SMD2 to SMD0 bits in UiMR register “000
(2) Set the SMD2 to SMD0 bits in UiMR register “001
(3) “1” is written to TE bit in the UiC1 register (reception enabled), regardless of the TE bit
G
4
J
7
a
o r
0 -
. n
u
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
NOTES:
2
(1) When the UFORM bit in the UiC0 register is set to "0" (LSB first)
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
CLK
T
R
CLK
T
R
3
p
0
X
X
X
X
, 1
1. This applies to the case where the CKPOL bit in the UiC0 register is set to "0" (transmit data output at the
0
D
D
(
D
D
M
i
i
i
i
i
i
2
falling edge and the receive data taken in at the rising edge of the transfer clock), the UiLCH bit in the UiC1
register is set to "0" (no reverse), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the PRYE bit
in the UiMR register is set to "1" (parity enabled).
0
1
0
6
7
C
2 /
page 188
, 8
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ST
ST
ST
1
6
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2 /
f o
D0
D
D
8
D
3
0
7
) B
7
8
5
D
D
D
D
1
1
6
6
D
D
D
D
2
2
5
5
D
D
D
D
3
3
4
4
D
D
D
D
4
4
3
3
2
2
” (Serial I/O disabled)
”, “101
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D
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D
5
5
2
2
2
D
D
D
D
”, “110
6
6
1
1
D
D
D
D
7
7
0
0
2
”
P
P
P
P
SP
SP
SP
SP
14.Serial I/O
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