M30280FAHP#D5 Renesas Electronics America, M30280FAHP#D5 Datasheet - Page 397
![IC M16C MCU FLASH 96K 80-LQFP](/photos/12/40/124063/m30280fahp_d5_sml.jpg)
M30280FAHP#D5
Manufacturer Part Number
M30280FAHP#D5
Description
IC M16C MCU FLASH 96K 80-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30280FAHP#D5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
For Use With
M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
M30280FAHP#D5A
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M
R
R
20.14 Flash Memory Version
e
E
1
. v
J
6
0
20.14.1 Functions to Inhibit Rewriting Flash Memory Rewrite
20.14.2 Stop Mode
20.14.3 Wait Mode
20.14.4 Low Power Dissipation Mode, On-Chip Oscillator Low Power Dissipation Mode
20.14.5 Writing Command and Data
20.14.6 Program Command
20.14.7 Operation Speed
20.14.8 Instructions Inhibited Against Use
C
2
9
2 /
ID codes are stored in addresses 0FFFDF
and 0FFFFB
in standard serial I/O mode.
The ROMCP register is mapped in address 0FFFFF
memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H)
of fixed vectors. The b3 to b0 in address 0FFFFF
When the microcomputer enters stop mode, execute the instruction which sets the CM10 bit to “1”(stop
mode) after setting the FMR01 bit to “0”(CPU rewrite mode disabled) and disabling the DMA transfer.
When the microcomputer enters wait mode, excute the WAIT instruction after setting the FMR01 bit to
“0”(CPU rewrite mode disabled).
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
Write the command code and data at even addresses.
Write ‘xx40
auto program operation (data program and verify) will start. Make sure the address value specified in the
first bus cycle is the same even address as the write address specified in the second bus cycle.
When CPU clock source is main clock, before entering CPU rewrite mode (EW mode 0 or 1), select 10
MHz or less for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1
register. Also, when CPU clock is f
(EW mode 0 or 1), set the ROCR3 to ROCR2 bits in the ROCR register to “divied by 4” or “divide by 8”.
On both cases, set the PM17 bit in the PM1 register to “1” (with wait state).
The following instructions cannot be used in EW mode 0 because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
0 .
B
0
0
• Program
• Block erase
8
0
G
4
J
7
a
o r
0 -
. n
u
2
3
p
0
, 1
0
(
16
M
2
16
0
1
’ in the first bus cycle and write data to the write address in the second bus cycle, and an
0
. If wrong data are written to theses addresses, the flash memory cannot be read or written
6
7
C
2 /
page 375
, 8
M
1
6
C
2 /
f o
8
3
) B
8
5
3
(ROC) on-chip oscillator clock, before entering CPU rewrite mode
16
, 0FFFE3
16
are reserved bits. Set these bits to “1111
16
. If wrong data is written to this address, the flash
16
, 0FFFEB
16
, 0FFFEF
16
, 0FFFF3
16
20. Precautions
, 0FFFF7
2
”.
16
,
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