M30280FAHP#D5 Renesas Electronics America, M30280FAHP#D5 Datasheet - Page 281
M30280FAHP#D5
Manufacturer Part Number
M30280FAHP#D5
Description
IC M16C MCU FLASH 96K 80-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30280FAHP#D5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
For Use With
M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
M30280FAHP#D5A
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16.1 I
16.2 I
e
E
1
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J
6
Figure 16.9 The Receive Data Storing Timing of S00 Register
0
The S00 register is an 8-bit data shift register to store a received data and to write a transmit data. When a
transmit data is written to the S00 register, the transmit data is synchronized with a SCL clock and the data
is transferred from bit 7. Then, every one bit of the data is transmitted, the register's content is shifted for
one bit to the left. When the SCL clock and the data is imported into the S00 register from bit 0. Every one
bit of the data is imported, the register's content is shifted for one bit to the left. Figure 16.9 shows the timing
to store the receive data to the S00 register.
The S00 register can be written when the ES0 bit in the S1D0 register is set to "1"(I
enabled). If the S00 register is written when the ES0 bit is set to "1" and the MST bit in the S10 register is set
to "1"(master mode), the bit counter is reset and the SCL clock is output. Write to the S00 register when the
START condition is generatedor when an "L" signal is applied to the SCL pin. The S00 register can be read
anytime regardless of the ES0 bit value.
The S0D0 register consists of the SAD6 to SAD0 bits, total of 7. At the addressing is formatted, slave
address is detected automatically and the 7-bit received address data is compared with the contents of
the SAD6 to SAD0 bits.
C
Internal S
Internal S
2
9
Shift clock
0 .
2 /
B
0
0
8
0
2
2
4
G
J
C0 Data Shift Register (S00 register)
S
C0 Address Register (S0D0 register)
S
7
a
DA
DA
CL
CL
o r
0 -
. n
u
2
3
p
0
, 1
0
(
M
2
0
1
0
6
7
C
2 /
page 259
, 8
M
tdfil
1
6
C
f o
2 /
8
3
) B
tdfil
8
5
tdsft
Storing data at shift clock rising edge.
16. MULTI-MASTER I
t
t
dfil : Noise elimination circuit delay time
dsf : Shift clock delay time
1 to 2 V
1 V
IIC
cycle
IIC
cycle
2
2
C0 bus interface
C bus INTERFACE
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