M30280FAHP#D5 Renesas Electronics America, M30280FAHP#D5 Datasheet - Page 99
![IC M16C MCU FLASH 96K 80-LQFP](/photos/12/40/124063/m30280fahp_d5_sml.jpg)
M30280FAHP#D5
Manufacturer Part Number
M30280FAHP#D5
Description
IC M16C MCU FLASH 96K 80-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30280FAHP#D5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
For Use With
M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
M30280FAHP#D5A
Available stocks
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Manufacturer
Quantity
Price
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M
R
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e
E
1
. v
Table 9.5 IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
J
6
Figure 9.6 Interrupt response time
0
9.4.1 Interrupt Response Time
9.4.2 Variation of IPL when Interrupt Request is Accepted
C
2
9
2 /
Figure 9.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes the time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of the time from when an interrupt request is generated till
when the instruction then executing is completed ((a) in Figure 9.6) and the time during which the inter-
rupt sequence is executed ((b) in Figure 9.6).
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 9.5 is set in the IPL. Shown in Table 9.5 are the IPL values of software and special interrupts
when they are accepted.
Watchdog timer, NMI, Oscillation stop and re-oscillation detection,
low voltage detection
Software, address match, DBC, single-step
0 .
B
0
0
8
0
G
4
J
7
a
o r
0 -
. n
u
2
3
p
Interrupt request generated
0
, 1
(a) The time from when an interrupt request is generated till when the instruction then
(b) The time during which the interrupt sequence is executed. For details, see the table
0
(
M
2
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
0
1
Interrupt sources
0
6
7
C
Interrupt vector address
_______
2 /
, 8
page 77
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Instruction
1
6
Even
Even
Odd
Odd
_________
C
(a)
2 /
f o
Interrupt response time
8
3
) B
8
5
Interrupt request acknowledged
Interrupt sequence
SP value
Even
Even
Odd
Odd
(b)
Without wait
18 cycles
19 cycles
19 cycles
20 cycles
interrupt routine
Instruction in
Level that is set to IPL
Time
Not changed
7
9. Interrupts
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