R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1124

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 22 A/D Converter
22.4.4
Timing of External Trigger Input
A/D conversion can be externally triggered. For unit 0, an external trigger is input from the
ADTRG0 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'110 in ADCR_0. For unit
1, an external trigger is input from the ADTRG1 pin when the TRGS1, TRGS0, and EXTRGS bits
are set to B'110 in ADCR_1. A/D conversion starts when the ADST bit in ADCSR is set to 1 on
the falling edge of the ADTRG pin. Other operations, in both single and scan modes, are the same
as when the ADST bit has been set to 1 by software. Figure 22.7 shows the timing.
Also, A/D conversion for multiple units can be externally triggered (multiple units can start
simultaneously). For units 0 and 1, an external trigger is input from the ADTRG0 pin when the
TRGS1, TRGS0, and EXTRGS bits are set to B'111 in ADCR_0 and ADCR_1. A/D conversion
starts when the ADST bit in ADCSR is set to 1 on the falling edge of the ADTRG0 pin. The
timing is different from the one when multiple units do not start simultaneously. Figure 22.8
shows the timing.
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 22.7 External Trigger Input Timing (TRGS1, TRGS0, and EXTRGS ≠ B'111)
Rev. 2.00 Oct. 21, 2009 Page 1090 of 1454
REJ09B0498-0200

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