R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 565

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3)
In this mode, the transfer destination address is specified in the destination address register
(EDDAR) and data in the cluster butter is written to the transfer destination. In this mode, the
TSEIE bit in the mode control register (EDMDR) must be set to 1.
One data access size to 32 bytes can be specified as a cluster size for the consecutive write
operation. When one data access size is specified as a cluster size, the cluster transfer write
address mode is used.
The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another
bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for the last write cycle. When an idle cycle is inserted before the last write cycle, the
ETEND signal is also output in the idle cycle.
In this mode, the EDACKE bit in EDMCR must be set to 0 to disable the EDACK pin output.
Figure 11.59 shows the data flow in the cluster transfer write address mode (from the cluster
buffer to the external memory), and figure 11.60 shows an example of the timing in cluster
transfer write address mode.
Cluster Transfer Write Address Mode (AMS = 1, DIRS = 1)
When initializing an area by the specified data, write the specified data from cluster buffer 0 into a register
sequentially. Then, specify the buffer size written in the register as a cluster size and the area to be initialized
as DAR, and then execute transfer in this mode.
LSI
Figure 11.59 Data Flow in Cluster Transfer Write Address Mode
Cluster buffer
(from Cluster Buffer to External Memory)
External data bus
EDDAR access
Rev. 2.00 Oct. 21, 2009 Page 531 of 1454
Section 11 EXDMA Controller (EXDMAC)
Transfer
destination
external
memory
REJ09B0498-0200