R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 118
R5F61665N50FPV
Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61665N50FPV.pdf
(1492 pages)
Specifications of R5F61665N50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 118 of 1492
- Download datasheet (8Mb)
Section 3 MCU Operating Modes
3.3.5
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on-
chip ROM is disabled.
The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas.
Ports D, E, and F function as an address bus, port H functions as a data bus, and parts of ports A
and B function as bus control signals. However, if any area is designated as a 16-bit access space
by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data
bus.
3.3.6
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on-
chip ROM is enabled.
The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas.
Ports D, E, and F function as input ports, but they can be used as an address bus by specifying the
data direction register (DDR) for each port. For details, see section 13, I/O Ports. Port H functions
as a data bus, and parts of ports A and B function as bus control signals. However, if any area is
designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits,
and ports H and I function as a data bus.
3.3.7
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on-
chip ROM is enabled.
All I/O ports can be used as general input/output ports. The external address space cannot be
accessed in the initial state, but setting the EXPE bit in the system control register (SYSCR) to 1
enables the external address space. After the external address space is enabled, ports D, E, and F
can be used as an address output bus and ports H and I as a data bus by specifying the data
direction register (DDR) for each port. When the external address space is not in use, ports J and
K can be used by setting the PCJKE bit in the port function control register D (PFCRD) to 1. For
details, see section 13, I/O Ports.
Rev. 2.00 Oct. 21, 2009 Page 84 of 1454
REJ09B0498-0200
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