R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 240

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
Rev. 2.00 Oct. 21, 2009 Page 206 of 1454
REJ09B0498-0200
Bit
6
5
Bit Name
RCDM
DDS
Initial
Value
0
0
R/W
R/W
R/W
Description
RAS Down Mode
Selects the RAS signal state while a DRAM access is
halted when a basic bus interface area or an on-chip
I/O register is accessed: keep the RAS signal low (RAS
down mode) and high (RAS up mode).
This bit is effective when BE = 1. Clearing this bit to 0
with RCDM = 1 in RAS down mode cancels the RAS
down mode and the RAS signal goes high.
If the RAS down mode is selected for the SDRAM
interface, the READ/WRIT command is issued without
issuance of the ACTV command when the same row
address is accessed consecutively.
0: RAS up mode when the DRAM/SDRAM is accessed
1: RAS down mode when the DRAM/SDRAM is
DMAC Single Address Transfer Option
Selects whether a DMAC single address transfer
through the DRAM/SDRAM interface is enabled only in
full access mode or is also enabled in fast-page access
mode.
When clearing the BE bit to 0 to disable a burst access
to the DRAM/SDRAM interface, a DMAC single address
transfer is performed in full access mode regardless of
this bit.
This bit does not affect an external access by other bus
masters or a DMAC dual address transfer. Setting this
bit to 1 changes the DACK output timing.
0: DMAC single address transfer through the
1: DMAC single address transfer through the
accessed
DRAM/SDRAM is enabled only in full access mode
DRAM/SDRAM is also enabled in fast-page access
mode