R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 288

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
9.7.3
Table 9.16 shows the pins used for the byte control SRAM interface.
In the byte control SRAM interface, write strobe signals (LHWR and LLWR) are output from the
byte select strobes. The RD/WR signal is used as a write enable signal.
Table 9.16 I/O Pins for Byte Control SRAM Interface
Rev. 2.00 Oct. 21, 2009 Page 254 of 1454
REJ09B0498-0200
Pin
AS/AH
CSn
RD
RD/WR
LHWR/LUB
LLWR/LLB
WAIT
A23 to A0
D15 to D0
I/O Pins Used for Byte Control SRAM Interface
A23 to A0
When Byte Control
SRAM is Specified
AS
CSn
RD
RD/WR
LUB
LLB
WAIT
D15 to D0
Name
Address
strobe
Chip select
Read strobe
Read/write
Lower-upper
byte select
Lower-lower
byte select
Wait
Address pin
Data pin
I/O
Output
Output
Output
Output
Output
Output
Input
Output
Input/
output
Function
Strobe signal indicating that the address
output on the address bus is valid when a
basic bus interface space or byte control
SRAM space is accessed
Strobe signal indicating that area n is
selected
Output enable for the SRAM when the byte
control SRAM space is accessed
Write enable signal for the SRAM when the
byte control SRAM space is accessed
Upper byte select when the 16-bit byte
control SRAM space is accessed
Lower byte select when the 16-bit byte
control SRAM space is accessed
Wait request signal used when an external
address space is accessed
Address output pin
Data input/output pin