UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 258

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

256
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
(3) Timer mode register mn (TMRmn)
TMRmn
Symbol
TMRmn sets an operation mode of channel n. It is used to select an operation clock (MCK), a count clock,
whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid edge of the
timer input, and an operation mode (interval, capture, event counter, one-count, or capture & one-count).
Rewriting TMRmn is prohibited when the register is in operation (when TEm = 1). However, bits 7 and 6
(CISmn1, CISmn0) can be rewritten even while the register is operating with some functions (when TEm = 1)
(for details, see 7.7 Operation of Timer Array Unit as Independent Channel and 7.8 Operation of Plural
Channels of Timer Array Unit).
TMRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Caution Be sure to clear bits 14, 13, 5, and 4 to “0”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7), mn = 00 to 07, 10 to 13
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Operation clock MCK is used by the edge detector. A count clock (TCLK) is generated depending on the setting of
the CCSmn bit.
Count clock TCLK is used for the timer/counter, output controller, and interrupt controller.
Only the even channel can be set as a master channel (MASTERmn = 1).
Be sure to use the odd channel as a slave channel (MASTERmn = 0).
Clear MASTERmn to 0 for a channel that is used with the single-operation function.
CKS
CCS
MAS
TER
CKS
mn
mn
mn
mn
15
0
1
0
1
0
1
Operation clock CKm0 set by TPSm register
Operation clock CKm1 set by TPSm register
Operation clock MCK specified by CKSmn bit
Valid edge of input signal input from TImn pin/subsystem clock divided by 4 (f
Operates in single-operation function or as slave channel in combination-operation function.
Operates as master channel in combination-operation function.
14
0
Selection of operation in single-operation function or as slave channel in combination-operation function
Figure 7-7. Format of Timer Mode Register mn (TMRmn) (1/3)
13
0
CCS
mn
12
/operation as master channel in combination-operation function of channel n
MAST
ERmn
11
CHAPTER 7 TIMER ARRAY UNIT
User’s Manual U18432EJ5V0UD
STS
mn2
Selection of operation clock (MCK) of channel n
10
Selection of count clock (TCLK) of channel n
STS
mn1
9
STS
mn0
8
After reset: 0000H
mn1
CIS
7
mn0
CIS
6
5
0
R/W
4
0
SUB
/4)
mn3
MD
3
mn2
MD
2
mn1
MD
1
mn0
MD
0