UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 939

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Standby
function
Reset
function
Power-on-
clear
circuit
Function
STOP mode
Block diagram of
reset function
Watchdog timer
overflow
RESF: Reset
control flag
register
Timing of
generation of
internal reset
signal (LVIOFF =
1)
Timing of
generation of
internal reset
signal (LVIOFF =
0)
Details of
Function
−
−
Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset,
the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the
HALT mode immediately after execution of the STOP instruction and the system
returns to the operating mode as soon as the wait time set using the oscillation
stabilization time select register (OSTS) has elapsed.
To use the peripheral hardware that stops operation in the STOP mode, and the
peripheral hardware for which the clock that stops oscillating in the STOP mode after
the STOP mode is released, restart the peripheral hardware.
To stop the internal low-speed oscillation clock in the STOP mode, use an option
byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0
(WDSTBYON) of 000C0H = 0), and then execute the STOP instruction.
To shorten oscillation stabilization time after the STOP mode is released when the
CPU operates with the high-speed system clock (X1 oscillation), temporarily switch
the CPU clock to the internal high-speed oscillation clock before the execution of the
STOP instruction. Before changing the CPU clock from the internal high-speed
oscillation clock to the high-speed system clock (X1 oscillation) after the STOP mode
is released, check the oscillation stabilization time with the oscillation stabilization
time counter status register (OSTC).
For an external reset, input a low level for 10
(If an external reset is effected upon power application, the period during which the
supply voltage is outside the operating range (V
μ
During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and
internal low-speed oscillation clock stop oscillating. External main system clock input
becomes invalid.
When the STOP mode is released by a reset, the RAM contents in the STOP mode
are held during reset input. However, because SFR and 2nd SFR are initialized, the
port pins become high-impedance, except for P130, which is set to low-level output.
An LVI circuit internal reset does not reset the LVI circuit.
A watchdog timer internal reset resets the watchdog timer.
Do not read data by a 1-bit memory manipulation instruction.
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF
flag may become 1 from the beginning depending on the power-on waveform.
If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset
signal is not released until the supply voltage (V
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
Set the low-voltage detector by software after the reset status is released (see
CHAPTER 22 LOW-VOLTAGE DETECTOR).
Set the low-voltage detector by software after the reset status is released (see
CHAPTER 22 LOW-VOLTAGE DETECTOR).
s. However, the low-level input may be continued before POC is released.)
APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
Cautions
μ
s or more to the RESET pin.
DD
DD
) exceeds 2.07 V ±0.2 V.
< 1.8 V) is not counted in the 10
p.688
p.690
p.690
p.690
p.695
p.695
p.695
p.696
p.697
p.703
p.703
pp.704,
705
p.704
p.706
p.707
(25/35)
937
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