UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 431
UPD78F1174AGF-GAT-AX
Manufacturer Part Number
UPD78F1174AGF-GAT-AX
Description
MCU 16BIT 78K0R/KX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1174AGF-GAT-AX.pdf
(968 pages)
Specifications of UPD78F1174AGF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
111
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1174AGF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Address: F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03),
(7) Serial flag clear trigger register mn (SIRmn)
Symbol
SIRmn
SIRmn is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn,
PEFmn, OVFmn) of serial status register mn is cleared to 0. Because SIRmn is a trigger register, it is cleared
immediately when the corresponding bit of SSRmn is cleared.
SIRmn can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SIRmn can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears this register to 0000H.
Caution Be sure to clear bits 15 to 3 to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
F0148H, F0149H (SIR10), F014AH, F014BH (SIR11),
F014CH, F014DH (SIR12), F014EH, F014FH (SIR13)
OVC
PEC
FEC
Tmn
Tmn
Tmn
15
0
1
0
1
0
1
0
2. When the SIRmn register is read, 0000H is always read.
No trigger operation
Clears the FEFmn bit of the SSRmn register to 0.
No trigger operation
Clears the PEFmn bit of the SSRmn register to 0.
No trigger operation
Clears the OVFmn bit of the SSRmn register to 0.
Figure 13-10. Format of Serial Flag Clear Trigger Register mn (SIRmn)
14
0
13
0
12
0
CHAPTER 13 SERIAL ARRAY UNIT
11
0
User’s Manual U18432EJ5V0UD
10
Clear trigger of overrun error flag of channel n
0
Clear trigger of parity error flag of channel n
Clear trigger of framing error of channel n
9
0
8
0
After reset: 0000H
7
0
6
0
5
0
R/W
4
0
3
0
FEC
Tmn
2
PEC
Tmn
1
OVC
Tmn
429
0
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