UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 553
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UPD78F1174AGF-GAT-AX
Manufacturer Part Number
UPD78F1174AGF-GAT-AX
Description
MCU 16BIT 78K0R/KX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1174AGF-GAT-AX.pdf
(968 pages)
Specifications of UPD78F1174AGF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
111
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1174AGF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Note1
SE
10
0
1
0
1
0
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
Remark X: Don’t care
102
MD
0
0
1
0
0
1
MD
101
0
1
0
0
1
0
2. When channel 1 of unit 1 is set to UART2 reception, this pin becomes an RxD2 function pin (refer to Table
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 13.3 (12) Serial output
5. When using UART2 transmission and reception in a pair, set channel 1 of unit 1 to UART2 reception (refer
6. Set the CKO10 bit to 1 before a start condition is generated. Clear the SO10 bit from 1 to 0 when the start
7. Set the CKO10 bit to 1 before a stop condition is generated. Clear the SO10 bit from 0 to 1 when the stop
SOE
13-10). In this case, operation stop mode or UART2 transmission must be selected for channel 0 of unit 1.
register m (SOm).
to Table 13-10).
condition is generated.
condition is generated.
10
0
0
1
1
0
1
1
1
0
1
1
1
0
Note4
Note4
Note4
Note4
Note4
Note6
Note4
Note4
Note4
Note7
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
SO
10
1
1
1
CKO
Note4
Note4
Note4
Note6
Note4
Note4
Note4
Note7
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
10
1
1
1
1
1
TXE
10
0
0
1
1
0
1
1
1
0
1
0
1
1
0
0
1
0
Table 13-9. Relationship between register settings and pins
(Channel 0 of unit 1: CSI20, UART2 transmission, IIC20)
RXE
10
0
1
0
1
1
0
1
0
0
0
1
0
0
1
0
0
1
142
Note3
Note3
PM
×
1
1
1
0
0
0
×
0
0
0
0
0
P142 PM
Note3
Note3
CHAPTER 13 SERIAL ARRAY UNIT
×
×
×
×
1
1
1
×
1
1
1
1
1
143
Note3
Note3
Note3
Note3
User’s Manual U18432EJ5V0UD
Note2
1
1
1
1
0
0
0
0
0
×
×
×
×
P143
Note2
Note3
Note3
Note3
Note3
×
×
×
×
×
×
×
×
1
1
1
1
1
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
144
PM
×
×
0
0
×
0
0
0
×
×
×
×
×
P144
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
×
×
1
1
×
1
1
1
×
×
×
×
×
transmission/reception
transmission/reception
IIC20 address field
Operation mode
Operation stop
transmission
start condition
stop condition
Master CSI20
Master CSI20
transmission
transmission
transmission
Slave CSI20
Slave CSI20
Master CSI20
transmission
Slave CSI20
IIC20 data
IIC20 data
reception
reception
reception
UART2
mode
IIC20
IIC20
Note5
SCL20/P142
(output)
(output)
(output)
SCK20/
SCK20
SCK20
SCK20
SCK20
SCK20
SCK20
SCL20
SCL20
SCL20
SCL20
SCL20
(input)
(input)
(input)
P142
P142
Pin Function
SI20/SDA20/
P143/RxD2
P143/RxD2
RxD2/P143
SDA20
SDA20
SDA20
SDA20
SDA20
P143
P143
P143
P143
SI20
SI20
SI20
SI20
Note2
TxD2/P144
551
SO20/
SO20
SO20
SO20
SO20
TxD2
P144
P144
P144
P144
P144
P144
P144
P144
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