MC9S12XA512VAG Freescale Semiconductor, MC9S12XA512VAG Datasheet - Page 1023

• Manufacturer Part Number: MC9S12XA512VAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512VAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR0AD1[15:8]
Reset
Reset
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port
register, otherwise the value at the pins is read.
24.0.5.59 Port AD1 Data Register 1 (PT1AD1)
Read: Anytime.
Write: Anytime.
This register is associated with AD1 pins PAD[7:0]. These pins can also be used as general purpose
I/O.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port
register, otherwise the value at the pins is read.
24.0.5.60 Port AD1 Data Direction Register 0 (DDR0AD1)
Read: Anytime.
Write: Anytime.
This register configures pin PAD[15:8] as either input or output.
Field
W
W
R
R
7–0
DDR0AD115 DDR0AD114 DDR0AD113 DDR0AD112 DDR0AD111 DDR0AD110 DDR0AD19
PT1AD17
7
0
7
0
Data Direction Port AD1 Register 0
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
Note: To use the digital input function on Port AD1 the ATD1 digital input enable register (ATD1DIEN0) has
read on PTAD10 register, when changing the DDR0AD1 register.
to be set to logic level “1”.
PT1AD16
Figure 24-62. Port AD1 Data Direction Register 0 (DDR0AD1)
0
0
6
6
Figure 24-61. Port AD1 Data Register 1 (PT1AD1)
Table 24-54. DDR0AD1 Field Descriptions
PT1AD15
5
0
5
0
PT1AD14
0
0
4
4
Description
PT1AD13
3
0
3
0
PT1AD12
0
0
2
2
PT1AD11
1
0
1
0
DDR0AD18
PT1AD10
0
0
0
0