MC9S12XA512VAG Freescale Semiconductor, MC9S12XA512VAG Datasheet - Page 98

• Manufacturer Part Number: MC9S12XA512VAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512VAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.4
2.4.1
2.4.1.1
The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased
flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers
a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,...
126,128 based on the SYNR register.
The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on
the difference between the output frequency and the target frequency. The PLL can change between
acquisition and tracking modes either automatically or manually.
The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency f
98
EXTAL
XTAL
supplied by:
Functional Description
Functional Blocks
Phase Locked Loop (PLL)
V
V
CONSUMPTION
Although it is possible to set the two dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If (PLLSEL = 1), Bus Clock = PLLCLK / 2
DDPLL
DD
OSCILLATOR
REDUCED
/V
SS
/V
SSPLL
OSCCLK
MONITOR
CRYSTAL
PLLCLK
Figure 2-16. PLL Functional Diagram
MC9S12XDP512 Data Sheet, Rev. 2.21
PROGRAMMABLE
REFDV <5:0>
REFERENCE
DIVIDER
=
PROGRAMMABLE
2 OSCCLK
SYN <5:0>
DIVIDER
CAUTION
LOOP
REFERENCE
FEEDBACK
----------------------------------- -
REFDV
SYNR
DETECTOR
DETECTOR
FILTER
LOOP
PHASE
LOCK
PDET
+
+
1
1
V
DDPLL
DOWN
UP
LOCK
CPUMP
XFC
PIN
Freescale Semiconductor
V
DDPLL
/V
SSPLL
VCO
PLLCLK
SCM
.