MC9S12XA512VAG Freescale Semiconductor, MC9S12XA512VAG Datasheet - Page 834

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MC9S12XA512VAG

Manufacturer Part Number
MC9S12XA512VAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12XA512VAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Operating Supply Voltage
0 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.13 ECLK Control Register (ECLKCTL)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
836
Reset values in emulation modes are identical to those of the target mode.
Reset
NECLK
Field
7
NS
NX
SS
ES
ST
EX
W
R
1
Dependent
NECLK
Mode
No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always
active in emulation modes and if enabled in all other operating modes.
0 ECLK enabled
1 ECLK disabled
0
1
0
0
1
0
7
= Unimplemented or Reserved
NCLKX2
1
1
1
1
1
1
1
6
Figure 22-15. ECLK Control Register (ECLKCTL)
Table 22-16. ECLKCTL Field Descriptions
0
0
0
0
0
0
0
0
5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
0
0
0
0
4
Description
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
EDIV1
0
0
0
0
0
0
0
1
Freescale Semiconductor
EDIV0
0
0
0
0
0
0
0
0
Single-Chip
Single-Chip
Single-Chip
Expanded
Expanded
Emulation
Emulation
Special
Special
Normal
Normal
Mode
Test

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