MC9S12XA512VAG Freescale Semiconductor, MC9S12XA512VAG Datasheet - Page 872

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MC9S12XA512VAG

Manufacturer Part Number
MC9S12XA512VAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12XA512VAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Operating Supply Voltage
0 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.63 Port AD0 Data Direction Register 1 (DDR1AD0)
Read: Anytime.
Write: Anytime.
This register configures pins PAD[07:00] as either input or output.
874
DDR1AD0[7:0]
Reset
Field
7–0
W
R
DDR1AD07
0
7
Data Direction Port AD0 Register 1
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
Note: To use the digital input function on port AD0 the ATD0 digital input enable register (ATD0DIEN) has to
read on PTAD01 register, when changing the DDR1AD0 register.
be set to logic level “1”.
DDR1AD06
Figure 22-65. Port AD0 Data Direction Register 1 (DDR1AD0)
0
6
Table 22-58. DDR1AD0 Field Descriptions
DDR1AD05
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
DDR1AD04
0
4
Description
DDR1AD03
0
3
DDR1AD02
0
2
DDR1AD01
Freescale Semiconductor
0
1
DDR1AD00
0
0

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