MC9S12XA512VAG Freescale Semiconductor, MC9S12XA512VAG Datasheet - Page 954

• Manufacturer Part Number: MC9S12XA512VAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512VAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with
Port J.
23.0.5.61 Port J Interrupt Flag Register (PIFJ)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSJ register. To clear this flag, write logic level “1” to the corresponding bit in the PIFJ
register. Writing a “0” has no effect.
23.0.5.62 Port AD0 Data Register 1 (PT1AD0)
Read: Anytime.
Write: Anytime.
956
PIEJ[7:4]
PIEJ[2:0]
PIFJ[7:4]
PIFJ[2:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
PT1AD07
PIFJ7
Interrupt Enable Port J
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
Interrupt Flags Port J
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0
0
7
7
Writing a logic level “1” clears the associated flag.
= Unimplemented or Reserved
PT1AD06
PIFJ6
0
0
6
6
Figure 23-63. Port J Interrupt Flag Register (PIFJ)
Figure 23-64. Port AD0 Data Register 1 (PT1AD0)
PT1AD05
Table 23-56. PIEJ Field Descriptions
Table 23-57. PIEJ Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
PIFJ5
0
0
5
5
PT1AD04
PIFJ4
0
0
4
4
Description
Description
PT1AD03
0
0
0
3
3
PT1AD02
PIFJ2
0
0
2
2
PT1AD01
Freescale Semiconductor
PIFJ1
0
0
1
1
PT1AD00
PIFJ0
0
0
0
0