MC9S12XA512VAG Freescale Semiconductor, MC9S12XA512VAG Datasheet - Page 855

• Manufacturer Part Number: MC9S12XA512VAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512VAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.2.40 Port P Data Direction Register (DDRP)
Read: Anytime.
Write: Anytime.
This register configures each port P pin as either input or output.
If the associated PWM channel or SPI module is enabled this register has no effect on the pins.
The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7–0
channel. Channel 7 can force the pin to input if the shutdown feature is enabled. Refer to PWM section for
details.
If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRP bits revert to controlling the I/O direction of a pin when the associated peripherals are disabled.
Freescale Semiconductor
DDRP[7:0]
Reset
Field
7–0
W
R
DDRP7
Data Direction Port P
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
7
on PTP or PTIP registers, when changing the DDRP register.
DDRP6
0
6
Figure 22-42. Port P Data Direction Register (DDRP)
Table 22-39. DDRP Field Descriptions
DDRP5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
DDRP4
0
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
DDRP3
0
3
DDRP2
0
2
DDRP1
0
1
DDRP0
0
0
857