MC9S12XA512VAG Freescale Semiconductor, MC9S12XA512VAG Datasheet - Page 628

• Manufacturer Part Number: MC9S12XA512VAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512VAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 17 Memory Mapping Control (S12XMMCV2)
The fixed 16K page from $4000–$7FFF (when ROMHM = 0) is the page number $FD.
The reset value of $FE ensures that there is linear Flash space available between addresses $4000 and
$FFFF out of reset.
The fixed 16K page from $C000-$FFFF is the page number $FF.
17.3.2.9
Read: Anytime
Write: Anytime
628
Address: 0x011C
PIX[7:0]
Reset
RWPE
Field
Field
AVIE
AVIF
7–0
7
1
0
W
R
RWPE
Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM
array pages is to be accessed in the Program Page Window.
RAM Write Protection Enable — This bit enables the RAM write protection mechanism. When the RWPE bit
is cleared, there is no write protection and any memory location is writable by the CPU module and the XGATE
module. When the RWPE bit is set the write protection mechanism is enabled and write access of the CPU or
to the XGATE RAM region. Write access performed by the XGATE module to outside of the XGATE RAM region
or the shared region is suppressed as well in this case.
0 RAM write protection check is disabled, region boundary registers can be written.
1 RAM write protection check is enabled, region boundary registers cannot be written.
CPU Access Violation Interrupt Enable — This bit enables the Access Violation Interrupt. If AVIE is set and
AVIF is set, an interrupt is generated.
0 CPU Access Violation Interrupt Disabled.
1 CPU Access Violation Interrupt Enabled.
CPU Access Violation Interrupt Flag — When set, this bit indicates that the CPU has tried to write a memory
location inside the XGATE RAM region. This flag can be reset by writing’1’ to the AVIF bit location.
0 No access violation by the CPU was detected.
1 Access violation by the CPU was detected.
RAM Write Protection Control Register (RAMWPC)
0
7
= Unimplemented or Reserved
Figure 17-17. RAM Write Protection Control Register (RAMWPC)
0
0
6
Table 17-14. RAMWPC Field Descriptions
Table 17-13. PPAGE Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
0
0
4
Description
Description
0
0
3
0
0
2
Freescale Semiconductor
AVIE
0
1
AVIF
0
0