C8051F537-IT Silicon Laboratories Inc, C8051F537-IT Datasheet - Page 144

• Manufacturer Part Number: C8051F537-IT
• Description: IC 8051 MCU 2K FLASH 20TSSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F53xr

Specifications of C8051F537-IT

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 336-1401

C8051F52x/F52xA/F53x/F53xA
15.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 15.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “18.1.3. Mode 2: 8-bit Coun-
ter/Timer with Auto-Reload” on page 183). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an exter-
nal input T1. The UART0 baud rate is determined by Equation 15.1-A and Equation 15.1-B.
Where T1
auto-reload mode reload value). Timer 1 clock frequency is selected as described in Section “18. Timers”
on page 181. A quick reference for typical baud rates and system clock frequencies is given in Table 15.1.
Note that the internal oscillator may still generate the system clock when the external oscillator is driving
Timer 1.
144
CLK
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (8-bit
Detected
Start
A)
B)
UartBaudRate
T1_Overflow_Rate
Figure 15.2. UART0 Baud Rate Logic
RX Timer
Equation 15.1. UART0 Baud Rate
Timer 1
TH1
TL1
=
Overflow
Overflow
Rev. 1.3
1
-- - x T1_Overflow_Rate
2
=
-------------------------- -
256 TH1
T1
–
CLK
2
2
UART
RX Clock
TX Clock