C8051F537-IT Silicon Laboratories Inc, C8051F537-IT Datasheet - Page 204

IC 8051 MCU 2K FLASH 20TSSOP

C8051F537-IT

Manufacturer Part Number
C8051F537-IT
Description
IC 8051 MCU 2K FLASH 20TSSOP
Manufacturer
Silicon Laboratories Inc
Series
C8051F53xr
Datasheets

Specifications of C8051F537-IT

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.25 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
336-1401

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F537-IT
Manufacturer:
Silicon Labs
Quantity:
135
C8051F52x/F52xA/F53x/F53xA
19.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 19.4, this results in a WDT
timeout interval of 3072 system clock cycles. Table 19.3 lists some example timeout intervals for typical
system clocks.
204
Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock source (with the CPS2-CPS0 bits).
Load PCA0CPL2 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to 1.
Notes:
System Clock (Hz)
1. Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L
2. Internal oscillator reset frequency.
24,500,000
24,500,000
24,500,000
18,432,000
18,432,000
18,432,000
11,059,200
11,059,200
11,059,200
Table 19.3. Watchdog Timer Timeout Intervals
3,062,500
3,062,500
3,062,500
value of 0x00 at the update time.
191,406
191,406
191,406
32,000
32,000
32,000
2
2
2
PCA0CPL2
Rev. 1.3
255
128
255
128
255
128
255
128
255
128
255
128
32
32
32
32
32
32
Timeout Interval (ms)
24576
12384
129.5
4109
2070
3168
32.1
16.2
42.7
21.5
71.1
35.8
33.1
257
530
4.1
5.5
9.2
1

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