C8051F537-IT Silicon Laboratories Inc, C8051F537-IT Datasheet - Page 210

• Manufacturer Part Number: C8051F537-IT
• Description: IC 8051 MCU 2K FLASH 20TSSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F53xr

Specifications of C8051F537-IT

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 336-1401

C8051F52x/F52xA/F53x/F53xA
20.2. Reset Pin Behavior
The reset behavior of C8051F52x/F53x differs from C8051F52xA/F53xA devices. The differences affect
the state of the RST pin during a VDD Monitor reset.
On C8051F52x/F53x devices, a V
C8051F52xA/F53xA devices, a V
condition.
20.3. Reset Time Delay
The reset time delay on C8051F52x/F53x devices differs from C8051F52xA/F53xA devices.
On C8051F52x/F53x devices, the reset time delay will be as long as 80 ms following a power-on reset,
meaning it can take up to 80 ms to begin code execution. Subsequent resets will not cause the long delay.
On C8051F52xA/F53xA devices, the startup time is around 350 µs.
20.4. UART Pins
The location of the pins used by the serial UART interface is different between C8051F52x/F53x and
C8051F52xA/F53xA devices.
On C8051F52x/F53x devices, the TX and RX pins used by the UART interface are mapped to the P0.3
(TX) and P0.4 (RX) pins. On C8051F52xA/F53xA, the TX and RX pins used by the UART interface are
mapped to the P0.4 (TX) and P0.5 (RX) pins.
Important Note: On C8051F52xA/53xA devices, the UART pins must be skipped if the UART is enabled
in order for peripherals to appear on port pins beyond the UART on the crossbar. For example, with the
SPI and UART enabled on the crossbar with the SPI on P1.0-P1.3, the UART pins must be skipped using
P0SKIP for the SPI pins to appear correctly.
20.5. LIN
The LIN peripheral behavior in C8051F52x/F53x devices is different than the behavior of
C8051F52xA/F53xA devices. The differences are:
20.5.1. Stop Bit Check
On C8051F52x/F53x devices, the stop bits of the fields in the LIN frame are not checked and no error is
generated if the stop bits could not be sent or received correctly. On C8051F52xA/F53xA devices, the stop
bits are checked, and an error will be generated if the stop bit was not sent or received correctly.
210
Figure 20.3. Device Package—DFN 10
DD
Monitor reset will pull the RST pin low for the duration of the brownout
DD
520A
BNAB
628+
This character identifies
the device
Monitor reset does not affect the state of the RST pin. On
Rev. 1.3